Physics-informed diffusion for chip design: enforcing constraints by construction, not filtering
A new arXiv preprint argues that generative models for semiconductor manufacturing must embed physical constraints architecturally, not filter invalid outputs after generation, and surveys emerging techniques including physics-informed diffusion and PDE-constrained VAEs.
Generative models are increasingly used to propose chip designs, synthetic data, and process recipes, yet semiconductor manufacturing imposes hard physical constraints that cannot be negotiated. A new arXiv preprint argues that generative AI for such constrained domains must enforce those rules by construction—baking lithography, transport, reaction, and device-physics constraints directly into the model architecture—rather than generating freely and discarding invalid samples afterward.
The paper identifies four integration patterns between generative models and physics-based simulators: physics-informed diffusion, PDE-constrained variational models, neural-operator priors, and conservation-law-respecting generative networks. These techniques connect to differentiable lithography, TCAD (technology computer-aided design), process simulation, and autonomous experimentation. The authors position semiconductor fabs as a uniquely demanding test case. A generated mask or process recipe that violates physical laws is not merely low quality—it is entirely unusable. In this setting, the distinction between constraint-by-construction and constraint-by-filtering becomes sharp and consequential.
The preprint proposes a research agenda centered on physics-fidelity benchmarks, differentiable simulator infrastructure, and multimodal foundation models for physical design and manufacturing. The authors frame the challenge as fundamentally computational: where plausibility is subjective, filtering suffices; where validity is analytical, architectural enforcement is necessary. The paper is a perspective piece surveying the emerging toolkit rather than reporting new empirical results.
What remains to be seen is whether the proposed architectures can scale to the full complexity of real fab workflows, and whether differentiable simulators can be made fast enough to train large generative models end-to-end. The next wave of work should deliver concrete benchmarks that measure physical validity rates and demonstrate that constraint-by-construction models outperform filter-after-the-fact baselines on real semiconductor design tasks.
